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Espressif Systems /ESP32-S2 /IO_MUX /PIN_CTRL

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Interpret as PIN_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PIN_CLK_OUT1 0PIN_CLK_OUT2 0PIN_CLK_OUT3 0SWITCH_PRT_NUM 0 (PAD_POWER_CTRL)PAD_POWER_CTRL

Description

Clock output configuration register

Fields

PIN_CLK_OUT1

Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT1. 15: disabled.
PIN_CLK_OUT2

Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT2. 15: disabled.
PIN_CLK_OUT3

Configure I2S0 clock output. 0: output I2S0 clock to CLK_OUT3. 15: disabled.
SWITCH_PRT_NUM

IO pin power switch delay, delay unit is one APB clock.
PAD_POWER_CTRL

Select power voltage for GPIO33 ~ GPIO37. 1: select VDD_SPI 1.8 V. 0: select VDD3P3_CPU 3.3 V.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data